1. UART controller with configurable baud-rate. This design is validated on multiple Xilinx FPGAs including the latest Spartan6 and Virtex6 families

  2. FPGA implementation of Connect6 game without using any processor. For details please refer to my FPT2011 paper, “A Threat Based Connect6 Implementation on FPGA”. An interactive simulator is also available to plat against the FPGA logic using Modelsim simulator.

  3. A processor free ICAP controller for Virtex6 FPGAs. For details please refer to my FPT 2012 paper,“A High Speed Open Source Controller for FPGA Partial Reconfiguration”

  4. An AXI based FPGA swich with can manage multiple physical interfaces such as PCIe, DRAM and Ethernet. For details please refer to my FPT 2013 paper,"System-Level FPGA Device Driver with High-Level Synthesis Support"

  5. ZyCAP : A high-performance ICAP controller and associated driver for Zynq SoCs